The present invention pertains to a configurable arbitration device, and more particularly to a method and apparatus for arbitrating bus access between devices where a normal bus arbitration signal pair is shared by two or more devices.
A bus system is defined generally as a series of communication lines coupled between a plurality of components. A typical bus system architecture is the Peripheral Component Interconnect (PCI) system Version 2.1, 1995 (PCI Special Interest Group, Portland, Oreg.). Referring to FIG. 1, an example of a bus system operated according to the PCI architecture is shown. In FIG. 1, a central processing unit (CPU) 1 is coupled to a host bus 3 having control, address and data lines. A first bridge circuit 5 (also referred to as a host/PCI bridge or north bridge) is coupled between host bus 3 and a PCI bus 7. The first bridge circuit 5 is flier coupled to a cache memory 9 and main memory 11. Coupled to the PCI bus are one or more PCI components such as a Small Computer Standard Interface (SCSI) Host Bus Adapter 13 (which in turn is coupled to a SCSI bus 14), a Local Area Network (LAN) Adapter 15 (which in turn is coupled to a LAN 16, an Expansion Bus bridge 17 (which in turn is coupled to an Expansion bus, such as an EISA bus 18), and a Graphics Adapter 19 (which in turn is coupled to a Video Frame Buffer 20). Clocking signals to a variety of the aforementioned devices can be supplied by a central clock control 21.
As is known in the art, arbitration circuitry is required to award control of a bus to one device. In the PCI system, as shown in FIG. 2, a PCI device (e.g., device 50a) obtains control of the PCI bus by first asserting its REQ# signal (the "#" sign indicates a signal that is negatively asserted). All of the PCI devices that can initiate transfers on the bus are coupled via individual REQ# signal lines to a conventional arbiter 51. Through the use of the appropriate GNT# signal line coupled between each PCI device and arbiter 51, arbiter 51 controls which of devices 50a-c is given control of the bus. There are several well-known arbitration protocols or schemes in the art. For example, in a "round-robin" arbitration scheme, a device that is given control of the bus is subsequently given a lower priority for the next arbitration. Thus, after device 50a is given control of the bus by arbiter 51, if device 50a seeks to immediately obtain control of the bus at the same time as another device, control will be given to the other device coupled to the bus (e.g., 50b). Accordingly, device 50b would now have the lowest priority in the system. Once a device is given control of the bus, it can then commence a data transfer with another device coupled to the PCI bus as is described in the aforementioned PCI bus architecture.
In FIG. 2, there are three devices 50a-c shown which have REQ# and GNT# lines coupled to arbiter 51. A chip set for implementing a PCI system may have only four REQ/GNT signal line pairs for ports coupled to the PCI bus. A port is defined as a physical slot (e.g., an expansion connector) for insertion of a device (e.g., a card) or a resource coupled to the motherboard. There may, however, be a need for more ports to have access to the PCI bus and the arbiter. Accordingly, there is a need for a method and apparatus that addresses the problem of giving more ports access to the REQ/GNT lines of a conventional arbiter. Since configurations for bus systems can change, there is also a need for a method and apparatus that allow for changing the configuration of the arbitration system.